Semiconductor device

ABSTRACT

A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese patent application No. 2004-161300 filed on May 31, 2004, the content of which is hereby incorporated by reference into this application.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and, more particularly, it relates to a technology which is effective when applied to the miniaturization of a semiconductor device.

In a conventional integrated circuit package (semiconductor device), a filter device is coupled to at least any one of a power supply line for supplying power to an integrated circuit packaged in the package and an earth line for a reduction in electromagnetic interference caused by the integrated circuit. In an embodiment, a plurality of filter capacitors are coupled between the power supply line and the earth line within or in the vicinity of a cavity in the package (see, e.g., Patent Document 1).

[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 11(1999)-312776 (FIG. 2)

SUMMARY OF THE INVENTION

As an example of a semiconductor device in which a common lead is disposed in taking measures against EMI or the like, there has been known a structure in which a ring-shaped common lead is disposed between a semiconductor chip and connection pads to serve as power supply lines and earth lines, such as the one shown in Patent Document 1 mentioned above. Specifically, wire bonding is performed with respect to the ring-shaped common lead serving as GNDs or the power supply lines for the shared use thereof.

In the semiconductor device having such a structure, the common lead is shared by all the GNDs and power supply lines so that the problem of noise resulting from the presence of common impedance occurs.

When the ring-shaped common lead is disposed, bumps as external terminals cannot be provided on the bottom portion of the chip so that the problem of the scaling up of the main body of the semiconductor device also occurs.

It is therefore an object of the present invention to provide a semiconductor device that can be miniaturized.

Another object of the present invention is to provide a semiconductor device the characteristics of which can be improved.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

A brief description will be given to the outline of the representative aspects of the present invention disclosed in the present application.

Specifically, one aspect of the present invention is a semiconductor device comprising: a wiring substrate having a main surface and a back surface opposite to the main surface; a semiconductor chip mounted over the main surface of the wiring substrate, connected electrically to the wiring substrate, and having a first circuit portion for amplifying an inputted signal and a second circuit portion for converting a frequency of the signal supplied from the first circuit portion; and a plurality of external terminals provided over the back surface of the wiring substrate, wherein a first common conductor portion connected electrically to the first circuit portion to supply a GND potential to the first circuit portion and a second common conductor portion connected electrically to the second circuit portion to supply the GND potential to the second circuit portion are provided over the wiring substrate and the first and second common conductor portions are separated from each other.

Another aspect of the present invention is a semiconductor device comprising: a wiring substrate having a main surface and a back surface opposite to the main surface; a semiconductor chip mounted over the main surface of the wiring substrate, connected electrically to the wiring substrate, and having a first circuit portion for amplifying an inputted signal, a second circuit portion for converting a frequency of the signal supplied from the first circuit portion, and a third circuit portion for converting a frequency of the supplied signal; and a plurality of external terminals provided over the back surface of the wiring substrate, wherein a first common conductor portion connected electrically to the first circuit portion to supply a GND potential to the first circuit portion, a second common conductor portion connected electrically to the second circuit portion to supply the GND potential to the second circuit portion, and a third common conductor portion connected electrically to the third circuit portion to supply the GND potential to the third circuit portion are provided over the wiring substrate and the first, second, and third common conductor portions are separated from each other.

Still another aspect of the present invention is a semiconductor device comprising: a wiring substrate having a main surface and a back surface opposite to the main surface; a semiconductor chip mounted over the main surface of the wiring substrate, connected electrically to the wiring substrate, and having a first circuit portion for amplifying an inputted signal and a plurality of other circuit portions separated from the first circuit portion; and a plurality of external terminals provided over the back surface of the wiring substrate, wherein a first common conductor portion connected electrically to the first circuit portion to supply a GND potential to the first circuit portion and other common conductor portions connected electrically to the plurality of other circuit portions to supply the GND potential to the respective other circuit portions are provided in separate relation over the wiring substrate, and the other common conductor portions are connected to a planar conductor portion provided over the main surface of the wiring substrate.

Yet another aspect of the present invention is a semiconductor device comprising: a semiconductor chip having a first circuit portion and a second circuit portion; a wiring substrate having a first common conductor portion connected to a plurality of bonding electrodes over the substrate and a second common conductor portion connected to a plurality of other bonding electrodes over the substrate; and a plurality of external terminals provided over a back surface of the wiring substrate, wherein surface electrodes for GND for the first circuit portion of the semiconductor chip are connected to the first common conductor portion over the wiring substrate, surface electrodes for GND for the second circuit portion of the semiconductor chip are connected to the second common conductor portion over the wiring substrate, and the first and second common conductor portions are connected to external terminals over the back surface of the wiring substrate.

The following is the brief description of effects achievable by the representative aspects of the invention disclosed in the present application.

Since the first common conductor portion for supplying the GND potential to the first circuit portion in the chip and the second common conductor portion for supplying the GND potential to the second circuit portion in the chip are provided over the wiring substrate and the first and second common conductor portions are separated from each other, it becomes possible to eliminate common impedance, while allowing each of the circuit blocks to have a common GND to be used therein. Thus, the shared use of the GND allows the miniaturization of the semiconductor device. By further dividing the GND correspondingly to the individual circuit blocks, it becomes possible to reduce common impedance and improve the characteristics of the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view showing an example of a structure of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a perspective view showing an example of the arrangement of terminals on the back surface of the semiconductor device shown in FIG. 1;

FIG. 3 is a plan view showing an example of a structure of circuit blocks in a semiconductor chip mounted on the semiconductor device shown in FIG. 1 and an example of the connecting condition thereof with bonding electrodes;

FIG. 4 is a plan view showing an example of a common GND pattern in a wiring layer on the top surface of a wiring substrate incorporated in the semiconductor device shown in FIG. 1;

FIG. 5 is a bottom view showing an example of a wiring pattern in a wiring layer on the back surface of the wiring substrate shown in FIG. 4;

FIG. 6 is a bottom view showing an example of the arrangement of the external terminals of the semiconductor device shown in FIG. 1;

FIG. 7 is a circuit block diagram showing an example of a circuit configuration in a wireless communication apparatus on which the semiconductor device shown in FIG. 1 is mounted;

FIG. 8 is a wiring diagram showing an example of a wiring pattern on a packaging substrate on which the semiconductor device shown in FIG. 1 is mounted;

FIG. 9 is a wiring diagram showing a wiring pattern on a packaging substrate as a comparative example to the packaging substrate according to the first embodiment shown in FIG. 8;

FIG. 10 is a cross-sectional view schematically showing an example of a structure in which the semiconductor device shown in FIG. 1 is mounted on the packaging substrate;

FIG. 11 is a plan view showing an example of a wiring pattern in a wiring layer on the top surface of a packaging substrate incorporated in a semiconductor device according to a second embodiment of the present invention;

FIG. 12 is a cross-sectional view showing a structure in which a semiconductor device as a variation using the wiring pattern shown in FIG. 11 is mounted and a plan view of a planar conductor portion;

FIG. 13 is a bottom view showing the arrangement of external terminals in the semiconductor device as the variation shown in FIG. 12; and

FIG. 14 is a circuit diagram showing an example of a no-leakage-current state in the semiconductor device as the variation shown in FIG. 12.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the embodiments shown below, the repeated description of the same or like parts will be omitted in principle unless particularly necessary.

In the following embodiments, a description will be given to the present invention by dividing it, if necessary for the sake of convenience, into a plurality of sections or embodiments. However, they are by no means irrelevant to each other unless shown particularly explicitly and are mutually related to each other such that one of the sections or embodiments is a variation or a detailed or complementary description of some or all of the others.

If the number and the like of elements (including the number, numerical value, amount, and range thereof) are referred to in the following embodiments, they are not limited to specific numbers unless shown particularly explicitly or unless they are obviously limited to specific numbers in principle. The number and the like of the elements may be not less than or not more than specific numbers.

Herein below, the embodiments of the present invention will be described in detail with reference to the drawings. Throughout the drawings for illustrating the embodiments, parts having the same functions are designated by the same reference numerals and the repeated description thereof will be omitted.

Embodiment 1

FIG. 1 is a perspective view showing an example of a structure of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a perspective view showing an example of the arrangement of terminals on the back surface of the semiconductor device shown in FIG. 1. FIG. 3 is a plan view showing an example of a structure of circuit blocks in a semiconductor chip mounted on the semiconductor device shown in FIG. 1 and an example of the connecting condition thereof with bonding electrodes. FIG. 4 is a plan view showing an example of a common GND pattern in a wiring layer on the top surface of a wiring substrate incorporated in the semiconductor device shown in FIG. 1. FIG. 5 is a bottom view showing an example of a wiring pattern in a wiring layer on the back surface of the wiring substrate shown in FIG. 4. FIG. 6 is a bottom view showing an example of the arrangement of the external terminals of the semiconductor device shown in FIG. 1. FIG. 7 is a circuit block diagram showing an example of a circuit configuration in a wireless communication apparatus on which the semiconductor device shown in FIG. 1 is mounted. FIG. 8 is a wiring diagram showing an example of a wiring pattern on a packaging substrate on which the semiconductor device shown in FIG. 1 is mounted. FIG. 9 is a wiring diagram showing a wiring pattern on a packaging substrate as a comparative example to the packaging substrate according to the first embodiment shown in FIG. 8. FIG. 10 is a cross-sectional view schematically showing an example of a structure in which the semiconductor device shown in FIG. 1 is mounted on the packaging substrate.

The semiconductor device according to the first embodiment shown in FIGS. 1 and 2 is an RF power module 4 of a BGA (Ball Grid Array) type in which a semiconductor chip 1 is mounted on the main surface 5 a of a package substrate 5 as a wiring substrate, as shown in FIG. 3, and ball electrodes 8 as a plurality of external terminals are provided in lines on the back surface 5 b of the package substrate 5, as shown in FIG. 2.

In the RF power module 4, the semiconductor chip 1 has been incorporated, as shown in FIG. 3, and pads 1 c as surface electrodes provided on the peripheral portion of the main surface 1 a of the semiconductor chip 1 are connected electrically to bonding electrodes 5 i provided on the peripheral portion of the main surface 5 a of the package substrate 5 in corresponding relation to the pads 1 c by using conductive wires 6. These bonding electrodes 5 i are further connected electrically to the ball electrodes 8 provided on the back surface 5 b of the package substrate 5 such that the semiconductor chip 1 operates by exchanging signals with the outside thereof via the ball electrodes 8 as the external terminals.

As shown in FIG. 1, the semiconductor chip 1 and the plurality of wires 6 are covered and molded with a molded element 7 formed from a molding resin.

The semiconductor chip 1 is formed from, e.g., silicon and the conductive wires 6 are, e.g., gold wires. The molded element 7 is obtained by, e.g., thermosetting an epoxy-based resin. The package substrate 5 is obtained by forming a resin substrate with, e.g., a plurality of wires (conductor portions) by using a copper foil or the like. The ball electrodes 8 are formed by, e.g., soldering or the like. However, these members are not limited to those made of the materials mentioned above and the materials and sizes thereof can be changed variably.

The RF power module 4 according to the first embodiment is a semiconductor package mounted on, e.g., a mobile wireless communication apparatus or the like so that it is required to be miniaturized.

To satisfy the requirement, the miniaturization of the RF power module 4 is intended by providing the ball electrodes 8 as external terminals which are smaller in number than the pads 1 c on the semiconductor chip 1, while the improvement of the characteristics of the RF power module 4 is intended by dividing the GND (ground) on the package substrate 5 correspondingly to each of the individual circuit blocks composed of a plurality of circuits provided on the semiconductor chip 1.

A description will be given next to a circuit configuration of the semiconductor chip 1 mounted on the RF power module 4. FIG. 3 shows the diagrammatic arrangement of the individual circuit portions on the semiconductor chip 1 and the connecting condition between the circuit portions and the bonding electrodes 5 i of the package substrate 5 via the wires 6.

The plurality of pads 1 c as the surface electrodes are aligned on the main surface 1 a of the semiconductor chip 1 along each of the edges thereof. The individual circuit portions are arranged in different regions internally of the pads 1 c. As shown in FIG. 3, a PGA 1 m as a logic circuit portion for control is disposed at the near center of the semiconductor chip 1 and a MIXer (mixer) 1 i and four LNAs (Low Noise Amplifiers) as first circuit portions 1 d, 1 e, 1 f, and 1 g are arranged sideways on the left side thereof. On the upper side, an RF VCO (second circuit portion) 1 j is positioned, while an RF Synthsiser 1 k, a DC/VCXO it, a Control Logic 1 u, an IF Synthsiser 1 v, and IF VCO 1 w are aligned on the right side in a descending order and a TX VCO (third circuit portion) 1 q and an LPF is are positioned on the lower side.

It is to be noted that the RF power module 4 according to the first embodiment has functions compatible with, e.g., a dual band communication system to allow communication between a plurality of communication apparatus using different communication methods (systems).

Specifically, e.g., the four LNAs 1 d, 1 e, 1 f, and 1 g corresponding to four frequency zones are provided on the semiconductor chip 1 to allow transmission and reception in four bands. The first LNA 1 d uses the PCS (Personal Communications Services) method and the frequency zone of, e.g., 1930 to 1990 MHz. The second LNA 1 e uses the DCS (Digital Communication System) method and the frequency zone of, e.g., 1805 to 1880 MHz. The third LNA 1 f uses the GSM (Global System for Mobile Communications) 90 method and the frequency zone of, e.g., 925 to 960 MHz. The fourth LNA 1 g uses the GSM (Global System for Mobile Communications) 85 method and the frequency zone of, e.g., 869 to 894 MHz.

Thus, the circuit configuration which allows transmission and reception in the four bands is provided.

A description will be given next to the characteristic portion of the RF power module 4 according to the first embodiment. In the RF power module 4, the GND on the package substrate 5 is provided in divided relation corresponding to the individual circuit blocks. However, each of the circuit blocks has a common GND used therein.

FIG. 4 shows an example of a wiring pattern of a surface layer wiring in the package substrate 5, in which the GND wire is divided correspondingly to the circuit block for the LNAs, the circuit block for the RF VCO, and the circuit block for the IF VCO, while the main circuit portion in each of the blocks is enclosed by the common GND wire within the block.

Specifically, the package substrate 5 is provided with: a first common GND wire (first common conductor portion) 5 c which is connected electrically to each of the first circuit portions LNAs 1 d, 1 e, 1 f, and 1 g to supply a GND potential to the first circuit portions; a second common GND wire (second common conductor portion) 5 d which is connected electrically to the RF VCO 1 j on the input side as the second circuit portion to supply the GND potential to the RF VCO 1 j; and a third common GND wire (third common conductor portion) 5 e which is connected electrically to the IF VCO 1 w on the output side as the third circuit portion to supply the GND potential to the IF VCO 1 w so that the first, second, and third common GND wires 5 c, 5 d, and 5 e are separated from each other. In each of the circuit blocks, the individual GND wire provided therein is used as the common GND wire.

Each of the LNAs 1 d, 1 e, 1 f, and 1 g as the first circuit portions amplifies an extremely weak signal inputted at a high frequency. The RF VCO 1 j on the input side as the second circuit portion converts the high frequency of the signal supplied from any of the LNAs 1 d, 1 e, 1 f, and 1 g to a low frequency. The IF VCO 1 w on the output side as the third circuit portion converts the low frequency of a signal supplied from a baseband in shown in FIG. 7 to a high frequency.

Consequently, if the RF VCO 1 j and the IF VCO 1 w are operating actively for frequency conversion in the vicinity of the LNAs 1 d, 1 e, 1 f, and 1 g in the state in which the GND is undivided and used commonly by the individual circuit blocks, the GND for each of the LNAs 1 d, 1 e, 1 f, and 1 g fluctuates so that the GND is not supplied stably. By contrast, if the GND is divided correspondingly to the individual circuit blocks as in the first embodiment, a structure free from common impedance can be obtained so that the GND for each of the circuit blocks is supplied stably. In other words, it becomes possible to reduce the common impedance and improve the characteristics of the RF power module 4.

In addition, the first common GND wire (first common conductor potion) 5 c disposed between each two adjacent ones of a plurality of wiring portions 5 f provided correspondingly to the individual LNAs 1 d, 1 e, 1 f, and 1 g, as shown in FIG. 4, shields noise occurring between the bands and thereby achieves a reduction in the influence of the noise on the wiring portions 5 f in the adjacent bands.

Since the plurality of wiring portions 5 f provided correspondingly to the individual LNAs 1 d, 1 e, 1 f, and 1 g are enclosed by the first common GND wire 5 c, the influence of noise occurring between bands on the wiring portions 5 f in the adjacent bands can be reduced reliably.

On the package substrate 5 of the RF power module 4, the GND wire in each of the circuit blocks is used as a common GND wire. In addition, the bonding electrodes 5 i which are connected to the pads 1 c for GND for each of the LNAs 1 d, 1 e, 1 f, and 1 g of the semiconductor chip 1 via the wires 6 are connected to the first common GND wire 5 c on the package substrate 5. The bonding electrodes 5 i which are connected to the pads 1 c for GND for the RF VCO 1 j of the semiconductor chip 1 via the wires 6 are also connected to the second common GND wire 5 d on the package substrate 5, while the bonding electrodes 5 i which are connected to the pads 1 c for GND for the IF VCO 1 w of the semiconductor chip 1 via the wires 6 is also connected to the third common GND wire Se on the package substrate 5. Furthermore, the first, second, and third, common GND wires 5 c, 5 d, and 5 e are connected to corresponding bump lands 5 h (ball electrodes 8) on the back surface 5 b of the package substrate 5.

Accordingly, the number of the bump lands 5 h on the back surface 5 b connected to wiring portions 5 j of back surface side shown in FIG. 5 is smaller than the number of the bonding electrodes 5 i in the surface layer wiring shown in FIG. 4 which is connected to wiring of back surface side via through-hole wires 5 g since the GND wire in each of the circuit blocks is the common GND wire used therein.

Specifically, the number of the ball electrodes 8 as the external terminals shown in FIG. 6, which are to be attached to the bump lands 5 h, is smaller than the number of the bonding electrodes 5 i connected to the pads 1 c on the semiconductor chip 1 on the package substrate 5 by using the wires 6. As a result, it becomes possible to reduce the number of the external terminals and miniaturize the RF power module 4.

As shown in FIG. 3, in the RF power module 4 according to the first embodiment, the pads 1 c on the semiconductor chip 1 and the bonding electrodes 5 i on the main surface 5 a of the package substrate 5 are connected electrically through coupling using the wires 6. At the time of coupling, some of the bonding electrodes 5 i for GND, which are among the plurality of bonding electrodes 5 i on the package substrate 5, are each connected to the two pads 1 c for GND in a one-to-two correspondence via the wires 6.

This corresponds to the fact that the number of the bonding electrodes 5 i on the package substrate 5 is smaller than the number of the pads 1 c on the semiconductor chip 1.

Conversely, the number of the pads 1 c on the semiconductor chip 1 is larger than the number of the bonding electrode 5 i on the package substrate 5, which allows easy design of a pad layout on the semiconductor chip 1.

In the case of the RF power module 4 according to the first embodiment, the number of the pads 1 c on the semiconductor chip 1 is 68 and the number of the bonding electrodes 5 i on the package substrate 5 is 61, as shown in FIG. 3, while the number of the ball electrodes 8 as the external terminals is 57 as shown in FIG. 6. Accordingly, the number of the pads 1 c on the semiconductor chip 1 is larger than the number of the bonding electrodes 5 i on the package substrate 5 and the number of the bonding electrodes 5 i on the package substrate 5 is larger than the number of the ball electrodes 8.

A description will be given next to the circuit operation of the RF power module 4 with reference to FIG. 7.

FIG. 7 is an example of a circuit block diagram in a wireless communication apparatus on which the RF power module 4 shown in FIG. 1 is mounted.

During reception, an extremely weak signal received from an antenna 2 (in the portion A) and having voice data (at, e.g., 50 kHz) and a carrier (in accordance with the band) is subjected to noise removal using an RF filter (Filter) 1 h (in the portion B) and the extremely weak signal is amplified in each of the LNAs 1 d, 1 e, 1 f, and 1 g (in the portion C). Further, a frequency serving as a reference, which is controlled by the RF Synthsiser 1 k (in the portion F) is supplied from the RF VCO 1 j (in the portion E) to the MIXer 1 i (in the portion D) and the carrier is removed from the signal supplied from each of the LNAs 1 d, 1 e, 1 f, and 1 g in the MIXer 1 i (the frequency is lowered).

Thereafter, only the voice data is supplied to the PGA 1 m (in the portion G) where the gain (Gain) is controlled in the PGA 1 m. The voice data with the controlled gain is then supplied to the baseband in (in the portion H) and voice is heard via a speaker.

During transmission, on the other hand, the voice (voice data) is uttered via a microphone and the frequency is raised (the carrier is imposed) in accordance with the band for transmission in the MIXer 1 p (in the portion I) and in the IF VCO 1 w (in the portion J). Then, the extremely weak signal is amplified in a PA (power amplifier) 1 r (in the portion K) and the signal having the voice data and the carrier is outputted again from the antenna 2 (in the portion A).

Thus, in the RF power module 4 according to the first embodiment, the first common GND wire 5 c for supplying the GND potential to each of the LNAs 1 d, 1 e, 1 f, and 1 g, the second common GND wire 5 d for supplying the GND potential to the RF VCO 1 j, and the third common GND wire 5 e for supplying the GND potential to the IF VCO 1 w are separated from each other in the signal flow. This prevents the individual circuit blocks from having common impedance, while allowing each of them to have a common GND to be used therein.

Since the GND has thus been divided correspondingly to the individual circuits, the characteristics of the RF power module 4 can be improved by reducing the common impedance.

By providing the common GND wire in each of the circuit blocks to be used therein, the RF power module 4 can be miniaturized.

As a result, it becomes possible to implement both the miniaturization of the RF power module 4 and the improvement of the characteristics thereof.

A description will be given next to a structure in which the RF power module 4 according to the first embodiment is mounted on the packaging substrate.

FIG. 10 is a schematic diagram showing an example of the structure in which the RF power module 4 is mounted on a packaging substrate 3. The packaging substrate 3 shown in FIG. 10 is a substrate having a multilayered wiring structure, in which the surface layer wiring is provided with a first common wire of substrate side (first common conductor portion of substrate side) 3 a connected electrically to the LNAs 1 d, 1 e, 1 f, and 1 g as the first circuit portions of the RF power module 4 and with a second common wire of substrate side 3 b connected electrically to the RF VCO 1 j as the second circuit portion. The first common wire of substrate side 3 a is connected electrically to the RF power module 4 via GND ball electrodes 8 a for the LNAs. The second common wire of substrate side 3 b is connected electrically to the RF power module 4 via GND balls 8 b for the VCOS.

In the packaging substrate 3, the first common wire of substrate side 3 a and the second common wire of substrate side 3 b are separated from each other in the surface layer wiring at least in the region corresponding to the bottom portion of the main body of the RF power module 4. This is because the surface layer wiring is connected electrically directly to the ball electrodes 8 of the RF power module 4 and is therefore particularly susceptible to the influence of noise so that the first common wire of substrate side 3 a and the second common wire of substrate side 3 b are preferably separated as shown in FIG. 10.

FIG. 8 shows a wiring pattern of the surface layer wiring of the packaging substrate 3, in which a plurality of terminals 3 e connected electrically to the ball electrodes 8 of the RF power module 4 are provided in accordance with the arrangement thereof. The first common wire of substrate side 3 a and the second common wire of substrate side 3 b are separated from each other in the region corresponding to the bottom portion of the main body of the RF power module 4.

That is, in the structure in which the RF power module 4 according to the first embodiment is mounted, the common GND wire for the LNAs is separated from the GND wires for the RF VCO 1 j and the IF VCO 1 w or for the other circuit portions such as the output and the synthesizers on the packaging substrate 3. This allows a reduction in the influence of noise received by each of the GND wires from the other GND wires.

As a result, each of the GNDs can be supplied stably.

Although the first common wire of substrate side 3 a and the second common wire of substrate side 3 b are connected electrically to internal wires 3 c for GND in inner layers via through-hole wires 3 d, these internal wires 3 c are also divided preferably in the region corresponding to the bottom portion of the main body of the RF power module 4, as shown in FIG. 10. However, the first common wire of substrate side 3 a and the second common wire of substrate side 3 b are connected electrically to each other at a portion at a distance from the region of the packaging substrate 3 on which the RF power module 4 is mounted and are connected to a common wire for GND.

Since the first common wire of substrate side 3 a is thus separated from the wires for GND for the other circuit portions, such as the second common wire of substrate side 3 b, in the region of the packaging substrate 3 located under the RF power module 4, the influence of noise received by each of the GND wires from the other GND wires can be reduced compared with that received in a substrate structure in which the first common wire of substrate side 3 a and the second common wire of substrate side 3 b, which is among the other circuit portions, are connected in the region on which the RF power module is mounted as shown in the comparative example of FIG. 9. Accordingly each of the GNDs can be supplied stably.

As a result, even in a structure in which the RF power module 3 is mounted on the packaging substrate 3, it becomes possible to improve the characteristics of the RF power module 4 by reducing the common impedance.

Embodiment 2

FIG. 11 is a plan view showing an example of a wiring pattern in a wiring layer on the top surface of a packaging substrate incorporated in a semiconductor device according to a second embodiment of the present invention. FIG. 12 is a cross-sectional view showing a structure in which a semiconductor device as a variation using the wiring pattern shown in FIG. 11 is mounted and a plan view of a planar conductor portion. FIG. 13 is a bottom view showing the arrangement of external terminals in the semiconductor device as the variation shown in FIG. 12. FIG. 14 is a circuit diagram showing an example of a no-leakage-current state in the semiconductor device as the variation shown in FIG. 12.

The semiconductor device according to the second embodiment is the same semiconductor package as the RF power module 4 according to the first embodiment, in which the GND common wires are provided in separate relation corresponding to the individual circuit blocks of the semiconductor chip 1 except that, on the package substrate 5, the first common GND wire (first common conductor portion) 5 c for supplying the GND potential to each of the LNAs 1 d, 1 e, 1 f, and 1 g as the first circuit portions of the semiconductor chip 1 is provided separately from fourth common GND wires (other common conductor portions) 5 k for supplying the GND potential to the plurality of other circuit portions (the circuit portions such as the RF VCO 1 j, the IF VCO 1 w, and the synthesizers). In addition, a planar GND wire 5 m as a planar conductor portion is formed at the near center portion of the main surface 5 a of the package substrate 5 a such that the wires for GND for the plurality of other circuit portions are connected to the planar GND wire 5 m via the fourth common GND wires 5 k.

Specifically, in dividing the GND common wire correspondingly to the individual circuit blocks of the semiconductor chip 1, the LNAs 1 d, 1 e, 1 f, and 1 g as the first circuit portions are separated from the other circuit portions so that the wire for GND is divided into two types which are the first common GND wire 5 c as the common GND wire for the LNAs and the fourth common GND wires 5 k as the common GND wires for the other circuit portions. Moreover, the fourth common GND wires 5 k for the other circuit portions are connected to the planar GND wire 5 m such that the common GND wire is shared among the other circuit portions.

On the LNA side of the package substrate 5, the first common GND wire 5 c is disposed between each adjacent two of the plurality of wiring portions 5 f provided correspondingly to the individual LNAs 1 d, 1 e, 1 f, and 1 g, as shown in FIG. 11, in the same manner as with the package substrate 5 of the RF power module 4 according to the first embodiment.

In the RF power module 4 using such a package substrate 5 according to the second embodiment, the plurality of ball electrodes 8 which are connected electrically to the planar GND wire 5 m are provided at positions corresponding to the planar GND wire 5 m on the back surface 5 b of the package substrate 5, as shown in FIGS. 12 and 13.

Specifically, ball electrodes 8 c for common GND which are the ball electrodes 8 connected electrically to the planar GND wire 5 m are positioned immediately under the planar GND wire 5 m. This makes it possible to reduce the potential of the power supply 9 shown in FIG. 14 to the GND for the package substrate 5 without causing a leakage current in either of the LNA side and the other-circuit-portion side (in the no leakage state shown in the portion P of FIG. 14), as shown in the current flow in the portion Q of FIG. 12.

Since the common GND wire is thus shared among the circuit portions other than the LNAs, the shielding effect on each of the circuits is weakened compared with that in the RF power module 4 according to the first embodiment, but the characteristics of the RF power module 4 according to the second embodiment can also be improved through the stabilization of the GND. In addition, the number of the external terminals of the RF power module 4 can be reduced since the planar GND wire 5 m allows the sharing of the common GND wire among the circuit portions other than the LNAs.

As shown in FIG. 12, the semiconductor chip 1 is mounted at a position above the planar GND wire 5 m over the main surface 5 a of the package substrate 5 with a die bonding material 10 being connected to the back surface 1 b of the semiconductor chip 1.

Although the invention achieved by the present inventors has been described specifically based on the embodiments thereof, the present invention is not limited to the embodiments thereof described above. It will easily be appreciated that various changes and modifications can be made in the invention without departing from the gist thereof.

For example, although the 4-band RF power module 4 provided with the low noise amplifiers (LNAs) corresponding to the four frequencies has been described above in each of the first and second embodiments, the number of bands for the RF power module 4 is not particularly limited.

Although each of the first and second embodiments has been described above by using, as an example, the case where the semiconductor device is of a BGA type having the ball electrodes 8 as the external terminals, the semiconductor device may also use external terminals other than the ball electrodes 8 provided that the semiconductor chip 1 is mounted on the wiring substrate and the GND wires for at least two circuit portions incorporated in the semiconductor chip 1 are provided in separate relation on the wiring substrate. For example, the semiconductor device described above may also be of an LGA (Land Grid Array) type.

The present invention is appropriate for use in an electronic device and a semiconductor device. 

1. A semiconductor device comprising: a wiring substrate having a main surface and a back surface opposite to the main surface; a semiconductor chip mounted over the main surface of said wiring substrate, electrically connected to the wiring substrate, and having a first circuit portion for amplifying an inputted signal and a second circuit portion for converting a frequency of the signal supplied from the first circuit portion; and a plurality of external terminals provided over the back surface of said wiring substrate, wherein a first common conductor portion electrically connected to said first circuit portion to supply a GND potential to said first circuit portion and a second common conductor portion electrically connected to said second circuit portion to supply the GND potential to said second circuit portion are provided over said wiring substrate, and said first and second common conductor portions are separated from each other.
 2. A semiconductor device comprising: a wiring substrate having a main surface and a back surface opposite to the main surface; a semiconductor chip mounted over the main surface of said wiring substrate, electrically connected to the wiring substrate, and having a first circuit portion for amplifying an inputted signal, a second circuit portion for converting a frequency of the signal supplied from the first circuit portion, and a third circuit portion for converting a frequency of the supplied signal; and a plurality of external terminals provided over the back surface of said wiring substrate, wherein a first common conductor portion electrically connected to said first circuit portion to supply a GND potential to said first circuit portion, a second common conductor portion electrically connected to said second circuit portion to supply the GND potential to said second circuit portion, and a third common conductor portion electrically connected to said third circuit portion to supply the GND potential to said third circuit portion are provided over said wiring substrate, and said first, second, and third common conductor portions are separated from each other.
 3. A semiconductor device according to claim 1, wherein a packaging substrate over which said semiconductor device is mounted has a first common conductor portion of substrate side which is connected electrically to said first circuit portion and a second common conductor portion of substrate side which is connected electrically to said second circuit portion, and said first and second common conductor portions of substrate side are separated from each other in surface layer wiring at least in a region of said packaging substrate corresponding to a bottom portion of said semiconductor device.
 4. A semiconductor device according to claim 1, wherein a plurality of low noise amplifiers to which signals at different frequencies are inputted are provided each as said first circuit portion in said semiconductor chip, and said first common conductor portion is disposed between each adjacent two of a plurality of wiring portions provided over the main surface of said wiring substrate correspondingly to said individual low noise amplifiers.
 5. A semiconductor device according to claim 4, wherein each of the plurality of wiring portions provided over said wiring substrate correspondingly to said individual low noise amplifiers is enclosed by said first common conductor portion.
 6. A semiconductor device according to claim 1, wherein said external terminals are smaller in number than bonding electrodes connected electrically to surface electrodes over said semiconductor chip over said wiring substrate.
 7. A semiconductor device according to claim 6, wherein said surface electrodes over said semiconductor chip are larger in number than said bonding electrodes over said wiring substrate.
 8. A semiconductor device comprising: a wiring substrate having a main surface and a back surface opposite to the main surface; a semiconductor chip mounted over the main surface of said wiring substrate, connected electrically to the wiring substrate, and having a first circuit portion for amplifying an inputted signal and a plurality of other circuit portions separated from said first circuit portion; and a plurality of external terminals provided over the back surface of said wiring substrate, wherein a first common conductor portion electrically connected to said first circuit portion to supply a GND potential to said first circuit portion and other common conductor portions electrically connected to said plurality of other circuit portions to supply the GND potential to said respective other circuit portions are provided in separate relation over said wiring substrate, and said other common conductor portions are connected to a planar conductor portion provided over the main surface of said wiring substrate.
 9. A semiconductor device according to claim 8, wherein said plurality of external terminals connected electrically to said planar conductor portion are provided at positions corresponding to said planar conductor portion over the back surface of said wiring substrate.
 10. A semiconductor device according to claim 8, wherein a plurality of low noise amplifiers to which signals at different frequencies are inputted are provided each as said first circuit portion in said semiconductor chip and said first common conductor portion is disposed between each adjacent two of a plurality of wiring portions provided over the main surface of said wiring substrate correspondingly to said individual low noise amplifiers.
 11. A semiconductor device comprising: a semiconductor chip having a first circuit portion and a second circuit portion; a wiring substrate having a first common conductor portion connected to a plurality of bonding electrodes over the substrate and a second common conductor portion connected to a plurality of other bonding electrodes over the substrate; and a plurality of external terminals provided over a back surface of said wiring substrate, wherein surface electrodes for GND for said first circuit portion of said semiconductor chip are connected to said first common conductor portion over said wiring substrate, surface electrodes for GND for said second circuit portion of said semiconductor chip are connected to said second common conductor portion over said wiring substrate, and said first and second common conductor portions are connected to external terminals over the back surface of said wiring substrate.
 12. A semiconductor device according to claim 11, wherein said external terminals are smaller in number than said bonding electrodes over said wiring substrate.
 13. A semiconductor device according to claim 12, wherein the surface electrodes connected to said bonding electrodes in said semiconductor chip are larger in number than said bonding electrodes. 